This page is currently under construction.

 

The interface part of this tool is developed in Cadence's Skills programming language. Inside an Opus layout window, this tool can be invoked after a particular polygon (wire) is highlighted. The physical dimension of the selected structure is computed and parsed to the LRC engine, which in turn performs the accurate 3-D field-based calculation. This tool is optimized for parasitic extraction of specific critical signals within a VLSI chip (such as clock routes) where the accuracy cannot be compromised. In addition, as a post-processor, this tool generates Spice netlists (in forms of subckt macros) for the equivalent, extracted RC, RLC, or LRCG (lossy) trees of up to three parallel active signal lines. The number of segments (stages) in a given tree is controlled by an user-defined error tolerance.

 

About  |   Products  |   New Items  |   Support  |   Contact