For an overview of Elecdra, please click the following set of presentation slides:

For a technical discussion on rule-based circuit network analysis as well as on Elecdra, please click here.

Highlights of Elecdra v2.10:

Input format: any Spice-compatible circuit netlist (with or without parasitic elements)

MOS directionality based on either built-in heuristics or verbatim from input netlists

Hierarchical creation of leaf cells via a stop-list of library cell names. Library cell port directionality augmented by reading in library cell models in Verilog format.

Support for selective-topology device size modification, ideal for non-uniform process shrinks.

Implemented close to 60 rules, 11 of which check for design warnings.

Rules compiled from static and dynamic precharged CMOS and BiCMOS VLSI designs.

Improved memory utilization, run-time, as well as rule-masking capability.

Platforms supported:

Sun OS and Solaris, HP-UX, SGI-Iris, and Linux.